This invention relates to the electronic circuits known as master-slave flip-flop circuits. More particularly, the invention relates to a master-slave flip-flop circuit incorporating a hold function without substantially increasing the propagation delay through the circuit. The invention also encompasses a method for holding data in a master-slave flip-flop circuit.
A master-slave flip-flop circuit is an essential building block in microprocessor design. FIG. 1 shows a prior art master-slave flip-flop circuit 100 which includes a master latch circuit 102 and a slave latch circuit 103. These two latch circuits operate on the same clock inputs, the signal xe2x80x9cCLKxe2x80x9d and its complementary or inverted signal xe2x80x9c_CLK. xe2x80x9d
Master latch circuit 102 includes a master input transmission gate 104, a master output inverter 105, and a master feedback circuit 106. Master input transmission gate 104 is connected between a master input node 110 and a master latch node 111, and is controlled by the clock signals CLK and _CLK. Master output inverter 105 is connected between master latch node 111 and an input to the slave latch circuit, slave input node 114. Feedback circuit 106 is connected to selectively apply feedback to the master latch node 111 under the control of the clock signals CLK and _CLK.
Slave latch circuit 103 comprises a latch circuit identical to master latch circuit 102, including a slave input transmission gate 124, a slave output inverter 125, and a slave feedback circuit 126. Slave input transmission gate 124 is connected between the slave input node 114 and a slave latch node 131, while slave output inverter 125 is connected between the slave latch node and a slave output which provides the output Q from master-slave flip-flop circuit 100. Slave feedback circuit 126 is connected to selectively apply feedback to slave latch node 131 under the control of the clock signals CLK and _CLK.
It will be noted by comparing the clock signals to the two latch circuits that the clock signals applied to slave latch circuit 103 are reversed with respect to the clock signals applied to master latch circuit 102. As the clock signal CLK goes high, master input transmission gate 104 is enabled so that master latch circuit 102 receives the data appearing at master input node 110, while slave input transmission gate 124 is disabled and slave latch circuit 103 stores data received on the previous clock half cycle. This data latched at slave latch circuit 103 is inverted by slave output inverter 125 to restore the polarity of the data and provide the circuit output Q. When the clock signal CLK goes low in the second half of the clock cycle, the states of master latch circuit 102 and slave latch circuit 103 are reversed. That is, when CLK goes low, master input transmission gate 104 is disabled and master latch circuit 102 stores the data which has been passed to the master latch circuit in the previous half clock cycle. At the same time, the low clock signal CLK and corresponding high signal _CLK enable slave input transmission gate 124 to pass the output from master latch circuit 102 to slave latch node 131.
Thus, in the first half of each clock cycle, input data is applied to master latch circuit 102 while slave latch circuit 103 stores data received from the master latch circuit in the last half of the previous clock cycle. In the second half of each clock cycle, master latch circuit 102 stores the data received in the first half cycle and slave latch circuit 103 to receives the output from the master latch circuit.
In many applications it is necessary to hold data at the output of a master-slave flip-flop circuit or control when new data is latched by the circuit. The prior art circuit shown in FIG. 1 shows hold circuit 140 added to master-slave flip-flop circuit 100 to facilitate this control over the operation of the master-slave flip-flop circuit. Hold circuit 140 comprises a multiplexer interposed between master input node 110 and a data input node which receives data D. The hold multiplexer 140 is implemented with two static AND gates 142 and 143, and a static NOR gate 144 with an inverter 145 to restore the polarity of the data D. A hold input comprising the signal xe2x80x9cHOLDxe2x80x9d and its complement xe2x80x9c_HOLDxe2x80x9d is used to control the two AND gates 142 and 143. When the HOLD signal is at a high logical state, and thus the _HOLD signal is at a low logical state, the data D is blocked at AND gate 142, and AND gate 143 passes a feedback signal derived from the master latch node 111. Thus, as long as the HOLD signal is high, the master latch circuit 102 cannot receive new data and simply holds data received in the clock cycle before the HOLD signal went to a high logical level. This data received in a previously clock cycle is also held latched at slave latch circuit 103 to maintain the previous data output at Q.
The hold capability in the prior art circuit shown in FIG. 1 is obtained at the cost of greatly increasing the propagation delay through the circuit. That is, since the hold multiplexer 140 is inserted in the data propagation path through the circuit, the multiplexer circuitry more than doubles the delay through the circuit as compared to the master-slave to flip-flop circuit without the hold multiplexer. Thus, the prior art hold arrangement shown in FIG. 1 incurs a severe performance penalty.
It is an object of the invention to provide a master-slave flip-flop circuit having the ability to selectively hold data while avoiding the performance penalty incurred in prior master-slave flip-flop circuits with hold capability. Another object of the invention is to provide a method of holding data in a master-slave flip-flop circuit without incurring a performance penalty.
A master-slave flip-flop circuit according to the invention utilizes a similar master and slave latch circuit arrangement to the circuit 100 shown in FIG. 1, but includes a hold control component interposed between the master latch node and slave input node. This hold control component blocks the transfer of data from the master latch node to the slave input node in response to a hold input. In the preferred form of the invention, the hold control component comprises a tri-state inverter having an input connected to the master latch node and an output connected to the slave input node. The hold input, comprising a high level hold signal and its complementary or inverted signal, controls the operation of the tri-state inverter to selectively disable the device from applying data to the slave input node from the master latch node. When the hold input is removed, that is, when the hold signal is at a low logical level and the complementary signal is at a high logical level, the master-slave flip-flop circuit operates in the normal fashion, receiving and latching new data in each clock cycle and applying that new data to the circuit output.
In an alternate form of the invention, the slave latch circuit includes a hold feedback component connected between a slave feedback node of the slave latch circuit and the slave input node. This hold feedback component applies a feedback signal to the slave input node in response to the hold input to help maintain the desired charge state at the slave input node while the hold input is asserted. The preferred hold feedback component comprises a tri-state inverter having an inverter input connected to the slave feedback node and an output connected to the slave input node. In this form of the invention, the same high level hold signal and complementary signal used to disable the hold control component are also used to enable the tri-state inverter to apply the desired feedback. However, in the absence of the hold input, that is, when the hold signal is at a logical low level and its complementary signal is at a logical high level, the tri-state inverter is disabled to block the feedback signal to the slave input node.
The method of holding data in a master-slave flip-flop circuit according to the invention includes applying data from a master latch node to the input of the slave latch circuit and then latching the data in a first clock cycle. The method then includes applying a hold input to isolate the slave input node from the master latch node in the following clock cycle. With the slave input node isolated from the master latch node in this hold condition, the slave latch circuit maintains the previously stored data without regard to the data applied to the master latch circuit of the master-slave flip-flop circuit.
The master-slave flip-flop circuit according to the present invention incorporates the hold capability without incurring any substantial performance penalty. Unlike the prior art circuit shown in FIG. 1, the hold capability in the present circuit is achieved with control elements embedded in the normal master-slave flip-flop circuitry, and without adding a muliplexing arrangement in the data propagation path. The embedded hold control elements according to the invention have no significant impact on the propagation delay through the master-slave flip-flop circuit.
These and other objects, advantages, and features of the invention will be apparent from the following description of the preferred embodiments, considered along with the accompanying drawings.